As is known and shown in FIG. 1, a ferroelectric cell 1 is formed by a MOS transistor 2 and a capacitor 3 which has, as dielectric, a ferroelectric material, for example PZT (PbZr1−xTixO3), SBT (SrBi2Ta2O9) or BLT (Bi4−xLaxTi3O12) or a paraelectric material, for example BST (BaSr1−xTixO3). More in particular, in the ferroelectric cell 1, the MOS transistor 2 is an N-channel transistor and has a drain terminal 4 connected to the bit line BL, a gate electrode 5 connected to a word line WL, and a source terminal 6 connected to a first electrode 7 of the capacitor 3. A second electrode 8 of the capacitor 3 is connected to a plate line PL.
The cell can store binary information by virtue of the hysteresis characteristics of the ferroelectric material comprised between the electrodes 7 and 8 and assuming, when no voltage is applied, two biasing states, according to the voltage previously applied to the electrodes of the capacitor 3.
The ferroelectric cells currently known may be in a strapped or in a stacked configuration. In the cells with strapped configuration, an example of which is shown in FIG. 2, the capacitor 3 is made on top of a field oxide region 10 delimiting an active area 11 of a substrate 12 which houses conductive regions—source region 14 and drain region 13—of the MOS transistor 2. In greater detail, the first electrode 7 of the capacitor 3 is arranged at the top and comprises a conductive region (for example of platinum) having a square or rectangular shape, connected to the drain region 13 of the MOS transistor 2 through a metal connection 16. The second electrode 8 of the capacitor 3 is arranged at the bottom and comprises a layer of conductive material (for example, platinum) which extends perpendicular to the sheet plane and forms a plate line PL, connected to the other capacitors of the adjacent cells. A dielectric region 17, of ferroelectric material, is comprised between the first electrode 7 and the second electrode 8. The gate electrode 5 of the MOS transistor 2 is of a polycrystalline silicon layer 18, which extends perpendicular to the sheet plane and forms a word line WL.
In the cells with stacked configuration, an example whereof is shown in FIG. 3, the capacitor 3 is formed on top of the active area 11, directly above the source region 14 of the transistor 2. In this case, the first electrode 7 of the capacitor 3 is arranged at the bottom and comprises a conductive region (for example, of platinum) having a square or rectangular shape, connected to the source region 14 through a contact 23 formed in an opening of a protective layer 24 (for example of BPSG), and the second electrode 8, of conductive material, is arranged at the top and is connected to the metal layer 25, thus defining the plate line PL.
Materials having barrier properties against oxygen (such as Ir/IrO2) 26 extend underneath the first electrode 7 and delimit at the top of the contact 23.
FIG. 4 shows the architecture of an array 28 of ferroelectric cells in the open bit line configuration. As may be seen, the ferroelectric cells 1 are arranged in rows and columns and are connected so that pairs of cells 27 are arranged parallel to the bit lines BL; the MOS transistors 2 of each pair of cells 27 have common drain regions, which are connected to the same bit line BL; and the capacitors 3 that belong to one pair of cells 27 adjacent in a direction parallel to the bit lines BL are connected to two adjacent plate lines PL.
The ferroelectric cells in stacked configuration are preferred since they satisfy the size scaling requirement of new CMOS technologies.
Various examples of cells in stacked configuration are disclosed in which both the electrodes 7, 8 and the dielectric region 17 are defined using a single mask and forming the plate line PL with a special metal layer. In another embodiment, the bottom electrode 7 comprises a conductive region formed separately, while the dielectric region 17 and the top electrode 8 are mutually aligned and formed with a single mask.
In all the above cases, etching at least one of the electrodes 7 and 8 with the same mask used for etching the ferroelectric material that constitutes the dielectric region 17 is critical. For example, during etching, compounds are formed that may redeposit along the edge of the capacitor and short circuit it. On the other hand, separate definition of the three parts forming the capacitor 3 (the two electrodes 7 and 8 and the dielectric region 17), which should solve the problem due to the fabrication processes, leads to an increase in the overall dimensions, thus going against the current trend of size scaling. In fact, when making the definition mask, it is necessary to take into account both the alignment tolerances and the minimum distances between the bottom electrode and the top electrode (for example, a distance of 0.4 μm). In particular, the bottom electrode 7 must be, on every side, larger than the dielectric region 17 by an amount at least equal to the alignment tolerance (for example, at least 0.2 μm). Likewise, the dielectric region 17 must be larger than the top electrode 8 by the same amount. Consequently, taking into account the minimum distance between the bottom electrodes 7, the overall dimensions of the capacitor 3, and consequently of the ferroelectric cells 1, are excessive.
In U.S. Pat. No. 6,300,654 granted to the present applicant, the above disadvantages are eliminated in a memory cell in stacked configuration. In practice, the distance between the dielectric regions of at least two ferroelectric memory cells adjacent in the direction of the bit lines is reduced. In particular, the dielectric region 17 is continuous and is shared between the two adjacent capacitors that belong to a pair of adjacent cells. In this way, the layout rules for scaling the capacitor are dictated only by the distance between two adjacent bottom electrodes and by the lateral space between the top and the bottom electrodes. This enables, for a same cell area, maximization of the working area of the capacitor as compared to the layout of the solution using three masks for defining the capacitor, wherein the dielectric region of cells that are adjacent in the direction of the bit lines is separated. Furthermore, the solution described in the above mentioned US patent causes an increase in the amplitude of the signal (proportional to the active area of the capacitor) supplied by each cell to the sense amplifier during reading.
The above known solution moreover affords the following advantages:                1) the ratio between the area of the capacitor and the total area of the cell is maximized; and        2) the critical points in the photolithography step and in the connections of the ferroelectric material are removed.        
The current trend is in the direction of further size scaling of the devices.